The present invention relates to a magnetic disc apparatus for use in an information processing apparatus such as a computer, and more particularly, to a magnetic disc apparatus including an LSI (large scale integrated circuit) for a magnetic disc apparatus which is capable of performing high speed read and write operations by parallelly reading and writing data from and to the magnetic disc apparatus, as well as effectively utilizing recording surfaces of magnetic discs by selecting a spare track or a spare sector in place of a defective track or a defective sector on the magnetic disc.
A conventional magnetic disc apparatus known as a parallel read and write type is described in Japanese Patent Application Laid-Open Publication No. 61-145767, which divides data belonging to a single sector on a data recording surface to simultaneously record the divided data in parallel, and simultaneously reads data recorded on respective data recording surfaces in parallel and synthesizes the same to data in sector units to thereby increase a data transfer speed.
As a counterpart of the above-mentioned parallel read and write type magnetic disc apparatus, there is a serial read and write type magnetic disc apparatus whose internal structure is shown in a block diagram of FIG. 17.
In FIG. 17, reference numeral 1 designates a host computer, 2 a magnetic disc apparatus, 3 a host interface control unit, 4 a buffer memory, 5 a disc control unit, 6 a microprocessor, 8 a recording and reproducing unit, 9 an encoder/decoder circuit, 11 a head circuit, 14 a parallel interface.
When parallel data of, for example, eight bits is supplied from the host computer 1 through the parallel interface 14, the parallel data is delivered in the magnetic disc apparatus 2 from the host interface control unit 3 to the disc control unit 5 where the parallel data is parallel-to-serial converted. The serially converted data is written one bit by one bit on a recording surface of a magnetic disc, not shown, through the encoder/decoder circuit 9 by the head circuit 11 as serial data. On the other hand, data serially read one bit by one bit is delivered through the encoder/decoder circuit 9 to the disc control unit 5. The disc control unit 5 converts the serial data to parallel form, and this parallel data is transferred to the host computer 1 through the host interface control unit 3 and the parallel interface 14.
FIG. 18 is a block diagram showing the disc control unit 5 as shown in FIG. 17 in detail.
In FIG. 18, reference numeral 24 designates a MPU (microprocessor unit) interface unit, 25 a host interface control unit, 7b a parallel-to-serial conversion unit, 27 a drive control unit, and 28 an ECC unit for detecting and correcting data errors. It will be appreciated that a serial data transmission path is established by data transmission paths from the parallel-to-serial conversion unit 7b to the drive control unit 27 and the ECC unit, and from the drive control unit 27 to the encoder/decoder unit 9 and thereafter.
FIG. 19 is a block diagram showing an internal structure of a conventional parallel read and write type magnetic disc apparatus. A magnetic disc apparatus 2 shown in this drawing comprises a plurality of disc-shaped recording surfaces constituting a single cylinder and read and write heads respectively corresponding to the respective recording surfaces, as shown in FIG. 20. When a disc control unit 5 receives m-bit parallel data from a host computer 1, the m-bit parallel data is output from disc control unit 5 as m-bit serial data on a single path (see FIG. 18). The m-bit serial data on a single path is converted into (m/2)-bit serial data on two paths to form two data trains by a single serial path to plural serial path conversion unit 7. The two data trains outputted as the results are encoded by the encoder/decoder circuit 9, and then they are assigned to two heads selected from a plurality of heads (by a head circuit 11). These two data trains are parallelly written on two disc-shaped recording surfaces corresponding to the selected two heads. On the other hand, when data is read from recording surfaces, two data trains are parallelly read from two disc-shaped recording surfaces corresponding to two heads. The read data trains are decoded, converted from (m/2)-bit serial data on two paths to m-bit serial data on a single path, and then integrated to m-bit parallel data by the disc control unit 5 and outputted to the host computer 1.
FIG. 20 is a lateral view showing a structure of magnetic discs and heads in the magnetic disc apparatus in FIG. 19.
In this drawing, five recording discs 51 are concentrically supported to constitute a cylinder, wherein the upper surface and the lower surface of each disc respectively constitute recording surfaces. Specifically, the upper surface and the lower surface of the respective five recording discs 51 are utilized as recording surfaces, so that there is a total of ten recording surfaces which correspond to a servo surface 52 and first to ninth data recording surfaces 53-1 to 53-9. Also, ten heads H are provided for the respective recording surfaces so as to be associated with one another.
FIG. 21 is a block diagram showing a circuit arrangement of the recording and reproducing unit 8 of the conventional magnetic disc apparatus shown in FIG. 19 in a data write operation.
In FIG. 21, the encoder/decoder unit 9 is shown as comprising n encoder circuits 16 while the head circuit 11 is shown as comprising n head amplifiers 17 and n heads 18 when writing data. If 2-bit parallel data is to be written, n is naturally 2. Reference numeral 15 designates a write clock generating circuit, 19 an NRZ (Non-Return to Zero) signal.
FIG. 22 is a block diagram showing a circuit arrangement of the recording and reproducing unit 8 of the conventional disc apparatus shown in FIG. 19 when data is read.
In FIG. 22, the encoder/decoder unit 9 is shown as comprising n decoder circuits 22 and n waveform shaper circuits 23, and the head circuit 11 is shown as comprising n head amplifiers 17 and n head 18 when reading data. However, as mentioned above, if 2-bit parallel data is to be read, n is naturally 2. Reference numeral 21 designates a phase synchronizing circuit.
The above-mentioned prior art is useful in achieving a high speed data transfer by performing parallel write and read operations. However, it does not consider a combination of data recording surfaces on which data divided from parallel data are to be stored, which results in always providing fixed combinations of the recording surfaces for a simultaneous read or write operation. For this reason, the prior art implies problems in a decrease of a storage capacity due to defective recording surfaces, which is remarkably important in a parallel read and write operation, and a deterioration in a data transfer speed caused by reassignment of spare tracks and spare sectors in place of defective tracks and defective sectors.
For example, as shown in the previously explained FIG. 20, in the magnetic disc apparatus of a dedicated servo system or a servo system using a servo surface employing five recording disc 51, assume that a two-bit parallel recording is performed where parallel data transferred from the host computer 1 is divided into two data trains, and a write or read operation of the two data trains is simultaneously carried out by the use of two data recording surfaces.
As shown in FIG. 20, nine out of ten recording surfaces are used as data recording surfaces (data recording surfaces 53-1 to 53-9). Therefore, if two surfaces are fixedly combined to be one unit for the two-bit parallel recording, one data recording surface inevitably remains unused and cannot be utilized for reading and writing data.
If the recording surfaces for the two-bit parallel recording are made by combinations of the data recording surfaces 53-1 and 53-2, 53-3 and 53-4, 53-5 and 53-6, and 53-7 and 53-8, the data recording surface 53-9 cannot be used for writing and reading data and remains unused.
On the above-mentioned occasion, referring to FIG. 23, assume that a track on the data recording surface 53-6 on a cylinder 57 is a defective track 56. Since the two-bit parallel recording simultaneously writes and reads on and from two data recording surfaces, if a defective track exists on either of the two recording surfaces and read and write operations are impossible thereon, read and write operations cannot be performed on a track on the non-defective recording surface.
In the case of FIG. 23, since a track on the data recording surface 53-6 is the defective track 56, even if a track on the data recording surface 53-5 is normal, the data recording surface 53-5 cannot be used. On such an occasion, a combination of two tracks, one of which is defective, should be replaced by or reassigned to a previously prepared combination of two spare tracks on a spare cylinder 61, as shown in FIG. 23.
Although there are two non-defective tracks (the data recording surfaces 53-5 and 53-9) on the same cylinders, since the combination of recording surfaces is fixed, the above free tracks (the data recording surfaces 53-5 and 53-9) cannot be combined, and previously combined two tracks determined as spare tracks should be used, which results in an extremely low efficiency and a cause of decrease in the storage capacity.
In this example, the two-bit parallel recording has been explained. If the number of bits constituting a parallel data train is increased (for example an eight-bit parallel recording), this tendency is further worsened. Specifically, in the eight-bit parallel recording, if one of eight tracks for storing data is defective, the remaining seven tracks cannot be used for writing and reading data.
Furthermore, in spite of the fact that the parallel recording is employed for a high speed data transfer, a defective track, if it exists, requires a seek operation for reassigning a spare track, whereby the above-mentioned high speed transfer may not be achieved. In the above explanation, the parallel recording has been assumed to be performed in track units, and the same result is derived if it is performed in sector units as shown in FIG. 24. To be specific, a spare sector area 59 used in place of a defective sector should be prepared in each track, and a reassignment requires a rotation delay for rotating the disc from a defective sector 58 to the spare sector area 59.
The above explanation has been made based on the assumption that there is at most one defective track in a single cylinder. Practically, it is rare that two or more defective tracks exist in a single cylinder.
Further, data transfer and reception between the disc control unit 5 and the encoder/decoder circuit 9, as shown in FIG. 17, are performed by two serial data to be read and written. For this reason, a disc control LSI employed in the disc control unit 5 is provided for each of serial data interfaces for read and write, wherein each data is treated as serial data.
Therefore, if a disc control is to be fulfilled by a single LSI, data between the disc control LSI and the encoder/decoder circuit 9 should be serial data, whereby a data transfer speed cannot be sufficiently increased.
On the other hand, if a plurality of disc control LSIs are employed, a processing performed by a microprocessor for controlling the disc control LSIs is excessive, which results in a large size of hardware, a difficulty in reducing size and providing a larger storage capacity, and an increase in cost.